The present invention relates to methods and apparatus for designing integrated circuits. More specifically, the invention relates to a method for generating design files in which the implementation of a design entity in a logic design may be specified. Even more specifically, a particular embodiment of the invention creates a design file using a design file template of a specified format, and instantiates I/O either from a graphics file (e.g., a block diagram) or text file (e.g., a VHDL file) under software control directly from the source file into the design file in the specified format.
Integrated circuits, and specifically programmable logic devices (PLDs), may be designed with a wide variety of software design tools which allow the designer to implement design entities either using a graphic editor to interconnect blocks and/or logic gates in a graphical user interface (GUI), or using a text editor to specify the implementation in a text based programming language such as VHDL or Verilog. Such text based design tools require a high level of programming knowledge and skill. Moreover, the complete (i.e., circuit level) specification of a particular design entity is typically a rather tedious and time consuming process with text based design tools. The designer must create a file with the proper formatting and then describe everything from the I/O of the design entity to its circuit level implementation, all in a complex, syntax-driven format. This workload is exacerbated by the fact that, even though much of the formatting is redundant from design file to design file, there is currently no convenient way of taking advantage of this redundancy.
It is therefore apparent that there is a need for a logic design tool which takes advantage of the formatting redundancies among design files to facilitate the generation of design files.